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High Performance DSP – Techniques and Processors
The design of high performance DSP Processors which are optimized for performance, power consumption and silicon area, has been facilitated by writing the parameterizable and synthesizable blocks at the structural level and utilizing a novel algorithm-to-architecture-to-DSP design process. The use of novel arithmetic techniques in conjunction with careful parameter selection enables the blocks to be customized in order that the final implementation produces the desired performance with minimized silicon area and power consumption.

Introduction
The development of high performance DSP with low power consumption and high functionality are the typical objectives of DSP designers. Achieving these goals in the permitted design time and testing the resultant designs is rapidly becoming a more difficult target.
The ability to reuse already existing parts of designs is attractive, when efforts are being made to reduce the design cycle time. This can only be facilitated if the functional blocks, which are to be reused, are of a generic nature that makes them applicable to a large number of designs. Generic cores, such as digital signal processors (DSPs), are applicable to the implementation of a wide range of functions.
The generic behavior however, has the drawback that it automatically means a reduction in the implementation characteristics for each function. The generic function will typically produce lower performance, higher power consumption and larger silicon area for the implementation of each function, than an optimized block would produce.
The development of generic cores of this nature can therefore be viewed as a compromise between the design of optimized solutions and a reduction in design time. The opportunities for design reuse are maximized by the function parameterisability, thereby dramatically reducing design times, without compromising on the performance, power consumption and silicon area of the final implementation.
We can summarize the High Performance DSP Requirements as follows:
Very high levels of DSP integer performance

Support for complex real-time synchronous applications (latency, predictable   throughput, synchronization)
Scalability to meet wide range of cost, power, performance.
Large memory and I/O bandwidth.
Friendly, compiler driven, programming environment.
Cost & power efficient solution.

High Performance DSP Processors (DSPs) Applications
High Performance DSPs are categorized with parameters such as Processing Speed more than 1Gops, Power consumption of upto 5Watts and Cost upto 50 US$. Their main areas of applications in Wireless domain include as the main processor inside 2G and 3G Wireless standards Base Stations (BTS). The Mobile Wireless Base Station Systems incorporate Receiver Algorithms, Smart Antennas, Wideband Transceiver architectures, Convolutional and Turbo Coding which is handled by none other than High Performance DSPs. Most common examples of High Performance DSP Architectures for 3G Wireless include Lucent DSP16210, Texas Instruments TMS320C6x, Starcore SC140. The Future trends for High Performance DSPs is MIMD (Multiple Instruction Multiple Data) Architecture based Processors. 

Dynamic Programming
The rapid growth of Wireless Communications has led to the demand for communication devices which can support multiple standards and have the capability of switching from one to another on-the-fly. For instance, a device which could support WLAN and WCDMA Standards would enable seamless communications in indoor LAN as well as outdoor Cellular environment. A key challenge involved in building of such a communication device is the design of a flexible hardware architecture that can ‘dynamically’ reconfigure itself to run different algorithms as required to support different standards. In particular the Viterbi decoding algorithm is used at the receiver of both WLAN and WCDMA systems to decode the convolutionally encoded data. The difference lies in encoding parameters such as constraint length, code rate and generator polynomials. As mobile and wireless communication becomes increasingly ubiquitous, the need for dynamic reconfigurability of hardware shall pose fundamental challenges for communication algorithm designers as well as hardware architects. In particular case of Viterbi decoder which is a crucial component at physical layer of most wireless communication systems.Dynamic Programming formulation is also proposed for optimal link adaptation in CDMA systems, with focus on delay constrained traffic
 


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